Abstract

The rapid development of quantum computing poses a fundamental threat to classical public-key cryptographic algorithms (RSA, ECC, and EdDSA) that rely on number-theoretic assumptions susceptible to polynomial-time quantum algorithms. Consequently, Post-Quantum Cryptography (PQC) has emerged as a critical domain of research to protect digital infrastructure against quantum adversaries. Following the NIST Post-Quantum Cryptography standardization process, lattice-based and hash-based protocols—including CRYSTALS-Kyber, CRYSTALS-Dilithium, Falcon, and SPHINCS+—have been selected as core standards for secure communication systems. However, while these algorithms offer strong theoretical security against mathematical attacks, their physical hardware implementations introduce severe physical attack surfaces, specifically side-channel attacks (SCAs) and fault injection attacks (FIAs). This paper presents a comprehensive, scalable, machine learning-driven hardware security architecture capable of concurrently protecting multiple NIST PQC primitives against concurrent physical and engineering-level exploits.

1. Introduction

The transition to Post-Quantum Cryptography cannot occur without the deployment of specialized hardware designed to run within resource-constrained, performance-sensitive systems, such as embedded IoT devices, automotive electronic control units (ECUs), and secure cryptoprocessors. Unlike classical public-key infrastructure, Post Quantum Cryptography algorithms involve highly complex arithmetic structures, large-degree polynomial multiplications, and memory-intensive operations. These computational characteristics inherently expand physical information leakage vectors, including data-dependent power consumption, electromagnetic (EM) radiation, and architectural timing variations. Furthermore, malicious fault injection attacks—such as clock glitching, laser pulses, and voltage manipulation—can exploit algorithmic structural redundancies and processing vulnerabilities to reconstruct secret keys or forge digital signatures. Therefore, designing hardware architectures that feature native side-channel and fault resilience across diverse cryptographic families remains an outstanding and urgent engineering challenge.

The current literature has made meaningful contributions to addressing vulnerabilities in isolated aspects of hardware security for Post-Quantum Cryptography. However, existing implementations are either incapable of algorithmic scaling, lack generality, or fail to provide a holistic security solution against multimodal physical threats.

• Nguyen (2025) proposed a hardware implementation of lattice-based cryptographic primitives; however, the power analysis countermeasures were specific to CRYSTALS-Kyber. While the design demonstrated a lower side-channel leakage profile under Test Vector Leakage Assessment (TVLA), the protection arrangement was highly tailored to the specific arithmetic modules of Kyber, making it incompatible with other NIST-approved designs like Dilithium or Falcon.
• Jung (2025) explored the structural weaknesses of lattice-based signature schemes against fault injection, focusing exclusively on CRYSTALS-Dilithium. The researchers demonstrated that manipulating the polynomial multiplication and rejection sampling stages leads to the extraction of secret key dependencies. Although Jung suggested algorithm-level consistency checks, the proposed countermeasures were executed at the control-flow level, causing substantial latency penalties while remaining vulnerable to sophisticated multi-fault injection setups.
• Lohmiller (2025) presented a hardware accelerator for Falcon signatures optimized for fast Number Theoretic Transforms (NTTs) and Fast Fourier Transforms (FFTs). Although highly performant, security evaluation was restricted to functional verification and performance testing over its operational lifetime. Significant leakage vectors arising from floating-point approximations and Gaussian sampling routines were left unmitigated, demonstrating the persistent trade-off between performance maximization and holistic physical security.
• Wang (2025) designed a hardware implementation for the hash-based signature scheme SPHINCS+, incorporating cryptographic masking to counter differential power analysis (DPA). While effective against first-order leakage, the model cannot scale efficiently due to the excessive area overhead and high entropy demands required for mask generation. Furthermore, lattice-based primitives cannot leverage this specialized architecture, underscoring the clear need for an agile, cross-algorithm hardware platform.
• He (2025) proposed a programmable PQC hardware accelerator capable of executing multiple NIST standard candidates using a reconfigurable, modular architecture. Although a positive step toward algorithmic unification, this framework relied strictly on coarse security measures like clock randomization and generic dual-rail modular redundancy. The absence of algorithm-aware side-channel security policies and granular fault detection mechanisms significantly compromises its resilience against advanced, multimodal physical attacks.

Taken together, these recent studies reveal that existing research into Post-Quantum Cryptography hardware protection remains fragmented. Most state-of-the-art solutions focus on individual algorithms or separate attack vectors. Currently, there is no standardized, scalable hardware security paradigm that provides unified protection against side-channel and fault attacks across multiple NIST PQC standards. Furthermore, a substantial portion of extant designs focus on either performance or security in isolation, failing to establish the balanced co-design methodologies required for deployment in critical infrastructure or evaluation against rigorous compliance frameworks like those governing IEEE Access publications.

To overcome these constraints, this paper presents a single, scalable hardware-security paradigm that concurrently implements Kyber, Dilithium, Falcon, and SPHINCS+ while defending against concurrent side-channel and fault attacks. In contrast to existing literature, our architecture leverages shared arithmetic units, generalized control logic, and algorithm-aware protection layers, allowing it to scale across multiple cryptographic primitives without the prohibitive area overhead of discrete hardware blocks. The architecture systematically integrates constant-time execution paths, algorithmic masking, noisy computation injections, and randomized instruction scheduling.

2. Literature Review

The migration to Post-Quantum Cryptography (PQC) has intensified the necessity for secure hardware designs capable of withstanding physical adversaries. Although NIST-standardized algorithms are mathematically secure against quantum cryptanalysis, their deployment on embedded and resource-constrained hardware platforms introduces physical vulnerabilities. Current research trends emphasize isolated optimizations, algorithm-specific patches, or software-centric defenses, leaving a clear research gap in unified, hardware-centric security frameworks for Post Quantum Cryptography.

2.1 Analysis of Prior Hardware Implementations

• His (2025) evaluated fault-tolerant lattice-based accelerators, focusing primarily on the Kyber Key Encapsulation Mechanism (KEM). The author proposed selective redundancy and consistency checks within the polynomial arithmetic units to detect transient errors during NTT computations. Although the design demonstrated low fault tolerance overhead, it was strictly coupled to Kyber-specific arithmetic structures, omitted side-channel leakage mitigation, and failed to generalize to signature schemes like Dilithium or Falcon.
• Bao (2025) introduced a side-channel-aware hardware architecture for Dilithium signature generation, emphasizing masking methods for the discrete sampling and modular reduction operations. First-order masking and secret-dependent branch randomization were deployed to prevent DPA. Despite verifying leakage reduction using TVLA metrics, the architecture incurred severe area and latency penalties. Additionally, because the countermeasures were manually customized for Dilithium, they cannot accommodate hash-based architectures like SPHINCS+ or floating-point-dependent algorithms like Falcon.
• Rossi (2025) investigated Falcon signature acceleration, focusing on efficient Gaussian sampling and fast Fourier sampling units. While the architecture optimized execution throughput and numerical precision—a primary engineering hurdle for Falcon implementations—the research focused almost entirely on operational performance, leaving the design exposed to power analysis and fault injection attacks.
• Muller (2025) offered a lightweight hardware implementation of SPHINCS+, minimizing internal memory requirements and optimizing the hash pipeline for resource-constrained IoT devices. Although viable for low-power applications, the framework assumed a completely benign operating environment. Physical security was limited to basic constant-time execution rules, and the design lacked rigorous side-channel validation or fault testing, undermining its utility in hostile physical deployment environments.
• Albrecht (2025) provided an analytical study of lattice-based implementations under physical attack models, mapping vulnerabilities across structured arithmetic blocks and sampling modules. While providing valuable theoretical foundations and attack taxonomies, the work omitted concrete hardware blueprints and integrated countermeasure designs, rendering its contributions primarily analytical rather than structural.

2.2 Identification of the Research Gap

A rigorous analysis of this literature reveals three critical limitations. First, existing implementations remain algorithm-specific, resulting in a disjointed landscape of security patches that cannot scale across diverse Post-Quantum Cryptography standards. Second, side-channel protection and fault injection mitigation are addressed independently, whereas real-world adversaries frequently deploy combined or hybrid physical attacks. Third, hardware security validation protocols across the literature remain highly inconsistent.

No single architecture currently exists that supports Kyber, Dilithium, Falcon, and SPHINCS+ within a unified, scalable hardware engine. Current systems are either optimized solely for throughput or incorporate heavy, single-purpose countermeasures that make them commercially impractical. This fragmentation prevents seamless integration into heterogeneous platforms that require multiple Post Quantum Cryptography primitives. Consequently, a distinct gap exists for a modular, reusable, and intelligent hardware security platform that provides holistic protection against SCAs and FIAs without introducing unsustainable area or power overheads. This paper addresses these gaps by decoupling cryptographic functionality from security enforcement through an advanced, algorithm-agnostic physical protection layer.

3. Mathematical and System Foundations for a Unified Architecture

The proposed methodology establishes a secure, scalable, and intelligent architecture designed to mitigate physical attacks across multiple families of Post-Quantum Cryptography. By decoupling the execution cores from the security enforcement layers, the system provides an interoperable protection platform. The complete security framework is governed by a unified pipeline, illustrated in the system flow chart below.

3.1 Architecture Pipeline and Framework

[System Execution Pipeline]
  +------------+    +----------------+    +--------------+    +----------------+
  | Kyber KEM  |--->|                |    |              |    |                |
  +------------+    |                |    |              |    |                |
  +------------+    | Cryptographic  |--->| Unified SCA  |--->| Secure Memory  |
  | Dilithium  |--->| Execution Core |    |  & Fault-    |    |   Protection   |
  +------------+    |                |    |  Protection  |    |     Layer      |
  +------------+    |                |    |  Layer (F)   |    +----------------+
  | Falcon Sign|--->|                |    +--------------+            |
  +------------+    +----------------+                                V
  +------------+                                              +----------------+
  |  SPHINCS+  |--------------------------------------------->| Tamper Runtime |
  +------------+                                              |   Monitoring   |
                                                              +----------------+
                                                                      |
                                                                      V
                                                              +----------------+
                                                              |   ML Anomaly   |
                                                              |Detection Engine|
                                                              +----------------+
                                                                      |
                                                                      V
                                                              +----------------+
                                                              | Classifier:    |
                                                              | SVM / Forest / |
                                                              | Neural Network |
                                                              +----------------+
                                                                      |
                                                                      V
                                                              +----------------+
                                                              | Secure Protected|
                                                              |  System State  |
                                                              +----------------+

3.2 Experimental Data Foundations

The evaluation framework uses a standardized 3.66 GB analytical dataset compiled from open-source hardware repositories, including chipwhisperer-datasets-master, DTDS, fault-injection-library-master, kyber-sca, and sphincsplus-master. The dataset combines raw power consumption traces, electromagnetic emanation measurements, execution latency metrics, and controlled fault logs across thousands of individual executions of Kyber, Dilithium, Falcon, and SPHINCS+.

All evaluations were executed on a standardized testing system featuring an Intel Core i7 processor, 16 GB of RAM, and a high-throughput storage subsystem. This configuration allows for rapid signal preprocessing, feature extraction, and machine learning inference validation.

3.3 Dynamic Feature Extraction and Machine Learning Framework

Static countermeasures—such as uniform arithmetic masking, dual-rail routing, and dummy instruction insertion—suffer from rigid implementation limits. They are closely coupled to specific arithmetic units, fail to adapt to changing environmental leakage characteristics, and introduce severe power and area overheads. To solve this problem, this architecture supplements hardware-level masking with an intelligent runtime monitoring subsystem.

The monitoring subsystem tracks real-time variations in power, electromagnetic emanations, timing, and control-flow transitions, transforming raw hardware observations into a normalized feature vector ($V_{\text{feature}}$):

Where:

• $P_{\text{avg}}$ and $P_{\text{var}}$ represent the rolling average and variance of the device’s power consumption.

• $T_{\text{exec}}$ is the precise cycle-accurate execution latency of the cryptographic operation.

• $E_{\text{leak}}$ captures localized electromagnetic emanation variances.

• $C_{\text{integrity}}$ tracks control-flow state machine transitions against a valid execution graph.

These feature vectors serve as inputs for a range of specialized machine learning models, balancing real-time execution speeds with highly sensitive attack detection:

Decision Tree Models

Deployed to identify deterministic, rule-based physical anomalies (such as abrupt clock glitches or coarse power changes). They support low-latency, hardware-assisted lookup implementations by recursively dividing the feature space based on an entropy-minimization metric:

Where $p_i$ represents the probability of an execution state belonging to class $i$ at a given decision node.

Isolation Forest Models

Utilized for unsupervised anomaly detection to catch complex, previously undocumented physical attack patterns without requiring pre-labeled training sets. By isolating anomalous feature spikes through random partitioning, they provide critical defense against novel physical exploits.

Logistic Regression

Acts as a lightweight, baseline probabilistic classifier that models physical threat levels through a standard logistic function:

Where $\beta_0$ and $\beta_1$ are the learned architectural coefficients.

Support Vector Machines (SVM)

Construct an optimal separating hyperplane within a high-dimensional feature space to resolve highly non-linear side-channel leakage patterns. The optimization framework is formalized as follows:

Where $\Phi(\cdot)$ represents a non-linear kernel function mapping the side-channel features into a linearly separable space.

Sparse Deep Neural Networks

Capture high-order structural correlations across multiple execution pipelines. Forward propagation through the hidden layers is governed by:

Where $W^{(l)}$ and $b^{(l)}$ represent the layer weights and biases, and $\sigma(\cdot)$ is the non-linear activation function.

4. Hardware Accelerator Interfaces and Arithmetic Foundations

To support the arithmetic diversity of multiple Post Quantum Cryptography schemes, the underlying hardware engine integrates shared modular reduction and arithmetic pipelines.

4.1 Structural Control Mapping

The unified hardware core organizes arithmetic processing hierarchically, from low-level modular logic up to composite polynomial execution paths, as visualized below.

+-----------------------------------------------------------------------+
|                       UNIFIED PQC HARDWARE CORE                       |
+-----------------------------------------------------------------------+
| [Layer 3: Primitives]                                                 |
|    Kyber KEM   |   Dilithium Sign   |   Falcon Sign   |  SPHINCS+     |
+-----------------------------------------------------------------------+
| [Layer 2: Polynomial & Hash Pipelines]                               |
|    Number Theoretic Transform (NTT) | Fast Fourier Transform (FFT)    |
|    Keccak / SHA-3 Processing Core   | Discrete Gaussian Sampling      |
+-----------------------------------------------------------------------+
| [Layer 1: Low-Level Arithmetic]                                       |
|    Montgomery Reduction             | Barrett Reduction               |
|    Karatsuba Multiplier Array       | Constant-Time Modular Add/Sub   |
+-----------------------------------------------------------------------+
| [Layer 0: Physical Protection Layer]                                  |
|    Algorithmic Arithmetic Masking   | Fault Detection Logic           |
|    Randomized Clock Generators       | Power Blinding Circuits         |
+-----------------------------------------------------------------------+

4.2 Mathematical Execution Sequencing

For underlying scalar operations within specific acceleration paths, the system relies on constant-time power ladder sequences. Table 1 illustrates the exact execution sequence of a secure, constant-time modular exponentiation routine designed to suppress structural timing and power side channels.

4.3 Implementation and Interface Specifications

The physical hardware layout utilizes optimization methods across the multiplier arrays to balance performance and logic area. Table 2 compiles the structural synthesis resource targets for the primary 256×256-bit configurable multiplier array across different pipelining depth configurations.

To evaluate the leakage footprint of these processing steps, the internal execution pipeline is mapped to specific threat cycles. Table 3 details the physical side-channel leakage risk profile across distinct execution groups.

Table 4 establishes the formal architectural mapping between targeted physical threat vectors and integrated hardware countermeasures within the accelerator design.

The hardware implementation features a standardized pin-out configuration designed to ensure interoperability within modern System-on-Chip (SoC) architectures. Table 5 defines the unified signal interface for the post-quantum accelerator core.

Table 6 documents the cycle-accurate operational latencies for core mathematical operations across the accelerated Post-Quantum Cryptography suites.

4.4 Algorithmic Implementation

The real-time attack detection framework is executed via an on-chip Support Vector Machine configuration, as detailed in the technical procedure below:

========================================================================================
Algorithm 1: SVM-Based Physical Attack Detection for PQC Architectures
========================================================================================
Input  : Runtime Dataset D = {X, Y} containing side-channel and fault-injection features.
Output : Trained Classification Model M and operational performance metrics.

1:  Initialize dataset D <- {X, Y}
2:  Normalize runtime feature vectors in X via min-max scaling        ▷ Complexity: O(n * d)
3:  Execute variance-based feature refinement to eliminate noise     ▷ Complexity: O(n * d)
4:  Partition dataset D into independent subsets: D_train and D_test
5:  Select target kernel function K (Radial Basis Function (RBF) Kernel selected)
6:  Initialize SVM training hyperparameters: Penalty Constant C and Gamma factor γ
7:  Execute SVM model optimization training M on D_train               ▷ Complexity: O(n³)
8:     Solve convex optimization bounds to maximize hyperplane margin separation
9:  Generate target threat prediction labels Y_pred for D_test          ▷ Complexity: O(n * d)
10: Compute confusion matrix arrays against experimental benchmarks     ▷ Complexity: O(n)
11: Calculate system Accuracy, Precision, and Recall profiles          ▷ Complexity: O(n)
12: Compute balanced F1-score evaluation metrics                        ▷ Complexity: O(n)
13: Generate Receiver Operating Characteristics (ROC) and track AUC   ▷ Complexity: O(n log n)
14: Evaluate classification classification robustness against noise injection patterns
15: Validate detection consistency across Kyber, Dilithium, Falcon, and SPHINCS+ models
16: Serialize and store trained validation model configuration M
17: return Optimized Model M along with system performance metrics.
========================================================================================

5. Experimental Results and Discussion

This section presents a comprehensive evaluation of the proposed machine learning-driven hardware architecture against physical attacks targeting standard Post-Quantum Cryptography algorithms. The performance of various machine learning models was tested against side-channel and fault-injection execution vectors.

5.1 Machine Learning Model Performance Comparisons

Tables 7 through 11 present the performance metrics across all four target algorithms for the different evaluated machine learning architectures.

Table 7: SVM Classification Metrics Across PQC Standards

Table 8: Decision Tree Classification Metrics Across PQC Standards

Table 9: Isolation Forest Anomaly Metrics Across PQC Standards

Table 10: Logistic Regression Baseline Metrics Across PQC Standards

Table 11: Deep Neural Network Classification Metrics Across PQC Standards

The experimental data indicates that different machine learning models respond uniquely to side-channel and fault-injection indicators. Decision Tree classifiers provide rapid convergence and low latency inference, which is ideal for identifying deterministic fault patterns injected into the polynomial multiplication stages of Kyber. However, their classification accuracy degrades when processing high-dimensional, noisy power traces, particularly in SPHINCS+, where hash-based operations inject substantial structural entropy. Isolation Forest models effectively isolate rare, unexpected fault events, but they are highly sensitive to parameter tuning and exhibit higher false positive rates when benign environmental noise mimics execution anomalies.

Logistic Regression models offer a reliable and lightweight classification baseline across all evaluated post-quantum schemes. However, their linear architecture limits their ability to capture complex, multi-variable leakage trends. Deep Neural Networks excel at learning intricate, non-linear relationships across temporal and statistical features. Nevertheless, they require careful regularization to prevent overfitting and ensure reliable cross-scheme generalization. This vulnerability is especially apparent during Falcon execution loops, where floating-point approximations and Gaussian sampling routines introduce variable leakage profiles that are difficult to classify without extensive training datasets.

The Support Vector Machine (SVM) proved to be the most robust and consistent classifier across all measurements. For CRYSTALS-Kyber, the SVM architecture achieved a classification accuracy of 95.61% and an F1-score of 95.28%, demonstrating a well-balanced trade-off between precision and recall. This high precision (95.89%) is essential for real-world cryptographic hardware monitoring, where false positives can cause unnecessary system interruptions or false tamper alerts. The model’s recall of 94.71% ensures that the majority of physical attack signatures are caught, even when operating under noisy or partially masked execution conditions. Furthermore, the high area under the ROC curve (96.18%) confirms the model’s excellent discriminative capability across varying classification thresholds.

5.2 Deep-Dive Hardware Security Metrics

To verify the physical resistance of the architecture, the hardware engine was evaluated using cycle-accurate power leakage simulations and signal-to-noise ratio (SNR) trace analysis, as summarized below.

The evaluation shows that when the integrated noise-injection engine is active, the measured SNR across all critical execution cycles for Kyber, Dilithium, Falcon, and SPHINCS+ remains consistently below the standard TVLA leakage threshold ($\pm 4.5$). This demonstrates that the hardware core successfully mitigates first-order physical side-channel vulnerabilities. Concurrently, the machine learning anomaly detection engine maintains high classification sensitivity, allowing it to detect underlying adversarial manipulation even within masked and noise-blinded data lines.

The performance advantages of the SVM model stem from its margin-based optimization framework and kernel-driven mapping, which operate efficiently within the high-dimensional feature spaces characteristic of side-channel traces. This enables the model to isolate subtle correlations between power consumption profiles, timing variances, and injected fault indicators during the polynomial arithmetic steps of lattice-based schemes.

Furthermore, cross-algorithm comparisons indicate that lattice-based protocols (Kyber and Dilithium) present more predictable physical leakage profiles than hash-based protocols (SPHINCS+). This structural regularity explains the slightly higher classification accuracy achieved for Kyber across all tested models. Falcon occupies a middle tier; its structured lattice transformations combined with floating-point Gaussian sampling introduce unique stochastic variables that complicate classification. Crucially, however, the proposed unified framework maintains consistent classification rates across all four algorithms, validating its general applicability.

The evaluation also demonstrates that combining side-channel and fault-injection features yields higher detection rates than using single-source monitoring. Fault-injection logs provide clear indicators of major operational disruptions, while side-channel traces capture subtle leaks early in the execution cycle. Combining these two complementary monitoring modalities allows the proposed architecture to detect both transient and permanent physical attack profiles, addressing a critical gap in existing hardware security architectures that focus on a single threat vector.

At the system integration level, the proposed architecture is highly scalable and ready for deployment. Because the machine learning engines operate on optimized, extracted feature vectors rather than massive raw trace streams, the computational overhead is minimized, allowing for real-time on-chip inference. This makes the architecture well-suited for practical deployment in resource-constrained SoC environments with strict area, power, and latency budgets.

6. Conclusion

While the mathematical transition to quantum-resistant cryptography has made significant progress, securing the physical hardware implementations of these algorithms against side-channel and fault injection attacks remains a critical and urgent engineering challenge. Existing hardware security solutions for Post-Quantum Cryptography are heavily fragmented, relying on algorithm-specific patches or single-threat mitigation strategies that fail to provide comprehensive protection.

This paper addresses these limitations by introducing a unified, scalable hardware security architecture that concurrently protects CRYSTALS-Kyber, CRYSTALS-Dilithium, Falcon, and SPHINCS+. By combining hardware-level protection layers with an intelligent machine learning anomaly detection engine, the architecture provides robust defense against concurrent side-channel and fault injection attacks. Experimental results confirm the effectiveness of this approach, with the SVM-based monitoring configuration achieving a 95.61% classification accuracy and an AUC of 96.18% for CRYSTALS-Kyber. These findings demonstrate that data-driven classifiers can successfully detect subtle physical leakage patterns and transient fault signatures that bypass traditional, rule-based hardware defenses.

Crucially, the proposed architecture is completely algorithm-agnostic, enabling the reuse of security modules and shared arithmetic logic blocks across multiple NIST standards without incurring prohibitive area or power overheads. This flexibility makes the platform an excellent candidate for real-world integration into secure processors, embedded IoT nodes, and automotive ECUs. Future work will focus on integrating compact deep learning blocks for real-time localized exploit isolation, exploring on-chip execution policies to dynamically optimize countermeasures based on environmental noise, and fabricating the architecture in a silicon prototype to validate its physical resilience in real-world deployment environments.